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Join the Ecosystem Pavilion and reach approximately 1,000 of director level and above executives from our customers!!

 Date: 9/26/2019

Time (PDT Time Zone)Plenary Session
08:00 - 9:00Registration & Ecosystem Pavilion
09:00 - 09:10Welcome Remarks
09:10 - 10:00TSMC Keynote Session
10:00 - 10:30Coffee Break & Ecosystem Pavilion

Time (PDT Time Zone)HPC & 3DICMobile & AutomotiveIoT & RF
10:30 - 11:00Emerging 3DIC Technology – From 2.5D to 3D Chips Integration
TSMC EDA & IP Design Enablement Updates
FinFET Technology for mmWave Applications
11:00 - 11:30Calibre in the Cloud – A Case study with AMD & Mentor
Functional Safety Analysis and Verification to meet the requirements of the Automotive market
Cadence Design Systems / Texas Instruments
Simplify Energy Efficient designs with cost-effective SoC Platform
Dolphin Design
11:30 - 12:00Optimizing FPGA-HBM in InFO_MS Structure
Cadence Design Systems / Xilinx
Thermal-induced reliability challenge and solution for adv. IC design
Flexible clocking solutions in advanced FinFet processes from 16nm to 5nm
Silicon Creations
12:00 - 13:00Lunch & Ecosystem Pavilion
13:00 - 13:30Chiplets solutions using CoWoS and InFO with 112Gbps Serdes and HBM2E/3.2Gbps for AI, HPC and Networking
Global Unichip Corporation
Overcome time-to-market and resource challenges: Hierarchical DFT for advanced node SoC design and production
Mentor: A Siemens Bunsiness / AMD
Developing AI-based Solutions for Chip Design
13:30 - 14:00Realizing Adaptable Compute Platform for AI/ML and 5G with Synopsys’ Fusion Design Platform
Xilinx / Synopsys
Comprehensive ESD/Latch-up reliability verification for IP & SoC Designs
NXP Semiconductor / Silicon Frontline Technology / Mentor
Reliable, Secure and Flexible OTP solutions in tsmc for IoT, AI and Automotive Applications
eMemory Technology Inc.
14:00 - 14:30HBM2E 4gbps I/O Design Techniques in 7nm & Below Nodes
Sensor fusion and ADAS SOC designs in TSMC 16FFC and N7
Cadence Design Systems
High-Speed Interface IP PAM-4 56G/112G Ethernet PHY IP for 400G and Beyond Hyperscale Data Centers
14:30 - 15:00Pushing 3GHz Performance of TSMC N7 Arm Neoverse N1 CPU using the Cadence Digital Flow
Cadence Design Systems / Arm
AWS Cloud enablement of design characterization flows using Synopsys® Primetime® & HSPICE®
Xilinx / Synopsys
Automotive IP Functional Safety – A Verification Challenge
Cadence Design Systems
15:00 - 15:30Coffee Break & Ecosystem Pavilion
15:30 - 16:00Large Scale Silicon Photonic Interconnects for Mass Market Adoption
Hewlett Packard Enterprise / Mentor, a Siemens Business
A New Era of MIPI D-PHY and C-PHY: Automotive Applications
M31 Technology
Best practices for Arm Cortex CPU energy efficient implementation flows
16:00 - 16:30Photonics Coming of Age: From Laboratory to Mainstream Applications
Cadence Design Systems / Lumerical
Integrating ADAS Controllers with Automotive-Grade IP for TSMC N7
The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm
Moortec Semiconductor Ltd
16:30 - 17:00Accelerating Semiconductor Design Flows with EDA on the Cloud
Amazon Web Services / Astera Labs
Arm automotive physical IP addresses new feature and functionality demands
Developing AI Accelerators for TSMC N7
17:00 - 17:30Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient implementations of the latest Arm® Processors in TSMC 7-nanometer FinFET (7FF) Process Technology
Arm / Synopsys
Cloud-based Characterization with Cadence Liberate Trio Characterization Suite and Arm-based Graviton
Cadence Design Systems / Arm
Optimize SOC designs while enabling faster tapeouts by closing chip integration DRC issues early in the design cycle
MaxLinear / Mentor, a Siemens Business
17:30 - 18:30Social Hour
Legal Notice
TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.